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general description the max1180 is a +3.3v, dual 10-bit, analog-to-digital converter (adc) featuring fully-differential wideband track-and-hold (t/h) inputs, driving two pipelined, nine- stage adcs. the max1180 is optimized for low-power, high-dynamic performance applications in imaging, instrumentation, and digital communication applica- tions. the max1180 operates from a single +2.7v to +3.6v supply, consuming only 413mw, while delivering a typical signal-to-noise ratio (snr) of 58.5db at an input frequency of 20mhz and a sampling rate of 105msps. the t/h driven input stages incorporate 400mhz (-3db) input amplifiers. the converters may also be operated with single-ended inputs. in addition to low operating power, the max1180 features a 2.8ma sleep mode, as well as a 1? power-down mode to conserve power during idle periods. an internal +2.048v precision bandgap reference sets the full-scale range of the adc. a flexible reference structure allows the use of the internal or external reference, if desired for applications requiring increased accuracy or a different input voltage range. the max1180 features parallel, cmos-compatible three-state outputs. the digital output format is set to two? complement or straight offset binary through a single control pin. the device provides for a separate output power supply of +1.7v to +3.6v for flexible inter- facing. the max1180 is available in a 7mm ? 7mm, 48- pin tqfp package, and is specified for the extended industrial (-40? to +85?) temperature range. pin-compatible higher and lower speed versions of the max1180 are also available. please refer to the max1181 data sheet for 80msps, the max1182 data sheet for 65msps, the max1183 data sheet for 40msps, and the max1184 data sheet for 20msps. in addition to these speed grades, this family includes a 20msps mul- tiplexed output version (max1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port. applications high resolution imaging i/q channel digitization multichannel if undersampling instrumentation video application features single +3.3v operation excellent dynamic performance: 58.5db snr at f in = 20mhz 72db sfdr at f in = 20mhz snr flat within 1db for f in = 202mhz to 100mhz low power: 125ma (normal operation) 2.8ma (sleep mode) 1? (shutdown mode) 0.02db gain and 0.25 phase matching (typ) wide ?vp-p differential analog input voltage range 400mhz, -3db input bandwidth on-chip +2.048v precision bandgap reference user-selectable output format?wo? complement or offset binary 48-pin tqfp package with exposed pad for improved thermal dissipation max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs ________________________________________________________________ maxim integrated products 1 d1a d0a ognd ov dd ov dd ognd d0b d1b d2b d3b d4b d5b com v dd gnd ina+ ina- v dd gnd inb- inb+ gnd v dd clk 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 tqfp-ep max1180 gnd v dd gnd v dd t/b sleep pd oe d9b d8b d7b d6b 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 refn refp refin refout d9a d8a d7a d6a d5a d4a d3a d2a pin configuration ordering information 19-2097; rev 0; 7/01 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp. range pin-package MAX1180ECM -40 c to +85 c 48 tqfp-ep functional diagram appears at end of data sheet.
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +3.3v, ov dd = +2.5v; 0.1f and 1.0f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 105.263mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , ov dd to gnd ...............................................-0.3v to +3.6v ognd to gnd.......................................................-0.3v to +0.3v ina+, ina-, inb+, inb- to gnd ...............................-0.3v to v dd refin, refout, refp, refn, clk, com to gnd ............................................-0.3v to (v dd + 0.3v) oe , pd, sleep, t/b, d9a d0a, d9b d0b to ognd ................................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 48-pin tqfp (derate 12.5mw/ c above +70 c).........1000mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 7.47mhz 0.75 2.5 lsb differential nonlinearity dnl f in = 7.47mhz, no missing codes guaranteed -1 0.4 +1.5 lsb offset error < 1 1.7 % fs gain error 0 2% fs analog input differential input voltage range v diff differential or single-ended inputs 1.0 v common-mode input voltage range v cm v dd /2 0.5 v input resistance r in switched capacitor load 20 k ? input capacitance c in 5pf conversion rate maximum clock frequency f clk 105 mhz data latency 5 clock cycles dynamic characteristics (f clk = 105.263mhz, 4096-point fft) f ina or b = 7.47mhz, t a = +25 c59 f ina or b = 20mhz, t a = +25 c 55 58.5 signal-to-noise ratio snr f ina or b = 50.078mhz (note 1) 58 db f ina or b = 7.47mhz, t a = +25 c 58.2 f ina or b = 20mhz, t a = +25 c 54.7 58.1 signal-to-noise and distortion (up to 5 th harmonic) sinad f ina or b = 50.078mhz (note 1) 57.6 db f ina or b = 7.47mhz, t a = +25 c72 f ina or b = 20mhz, t a = +25 c6072 spurious-free dynamic range sfdr f ina or b = 50.078mhz, (note 1) 70 dbc f ina or b = 7.47mhz -75 f ina or b = 20mhz -75 third-harmonic distortion hd3 f ina or b = 50.078mhz (note 1) -73 dbc
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +3.3v, ov dd = +2.5v; 0.1f and 1.0f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 105.263mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units intermodulation distortion (first five odd-order imds) imd f ina or b = 38.055mhz at -6.5db fs f ina or b = 42.926mhz at -6.5db fs (note 2) -74 dbc f ina or b = 7.47mhz, t a = +25 c -71 f ina or b = 20mhz, t a = +25 c -70 -59 total harmonic distortion (first five harmonics) thd f ina or b = 50.078mhz, (note 1) -69 dbc small-signal bandwidth input at -20db fs, differential inputs 500 mhz full-power bandwidth fpbw input at -0.5db fs, differential inputs 400 mhz aperture delay t ad 1ns aperture jitter t aj 2ps rms overdrive recovery time for 1.5 ? full-scale input 2 ns differential gain 1% differential phase 0.25 degrees output noise ina+ = ina- = inb+ = inb- = com 0.2 lsb rms internal reference reference output voltage refout 2.048 3% v reference temperature coefficient tc ref 60 ppm/ c load regulation 1.25 mv/ma buffered external reference (v refin = +2.048v) refin input voltage v refin 2.048 v positive reference output voltage v refp 2.162 v negative reference output voltage v refn 1.138 v differential reference output voltage range ? v ref ? v ref = v refp - v refn 0.98 1.024 1.07 v refin resistance r refin >50 m ? maximum refp, com source current i source 5ma maximum refp, com sink current i sink -250 a maximum refn source current i source 250 a maximum refn sink current i sink -5 ma
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units unbuffered external reference (v refin = agnd, reference voltage applied to refp, refn, and com ) refp, refn input resistance r refp, r refn measured between refp and com and refn and com 4k ? differential reference input voltage range ? v ref ? v ref = v refp - v refn 1.024 10% v com input voltage range v com v dd /2 10% v refp input voltage v refp v com + ? v ref /2 v refn input voltage v refn v com - ? v ref /2 v digital inputs (clk, pd, oe , sleep, t/b) clk 0.8 x v dd input high threshold v ih pd, oe , sleep, t/b 0.8 x ov dd v clk 0.2 x v dd input low threshold v il pd, oe , sleep, t/b 0.2 x ov dd v input hysteresis v hyst 0.1 v i ih v ih = ov dd or v dd (clk) 5 input leakage i il v il = 0 5 a input capacitance c in 5pf digital outputs (d9a d0a, d9b d0b) output voltage low v ol i sink = -200a 0.2 v output voltage high v oh i source = 200a ov dd - 0.2 v three-state leakage current i leak oe = ov dd 10 a three-state output capacitance c out oe = ov dd 5pf power requirements analog supply voltage range v dd 2.7 3.3 3.6 v output supply voltage range ov dd 1.7 2.5 3.6 v operating, f ina or b = 20mhz at -0.5db fs 125 155 sleep mode 2.8 ma analog supply current i vdd shutdown, clock idle, pd = oe = ov dd 115a electrical characteristics (continued) (v dd = +3.3v, ov dd = +2.5v; 0.1f and 1.0f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 105.263mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.)
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units operating, c l = 15pf , f ina or b = 20mhz at -0.5db fs 15 ma sleep mode 100 a output supply current i ovdd shutdown, clock idle, pd = oe = ov dd 210a operating, f ina or b = 20mhz at -0.5db fs 413 511 mw sleep mode 9.2 power dissipation pdiss shutdown, clock idle, pd = oe = ov dd 350 w offset 0.2 mv/v power-supply rejection ratio psrr gain 0.1 %/v timing characteristics clk rise to output data valid t do figure 3 (note 3) 5 8 ns output enable time t enable figure 4 10 ns output disable time t disable figure 4 1.5 ns clk pulse width high t ch figure 3, clock period: 9.5ns 4.75 1.5 ns clk pulse width low t cl figure 3, clock period: 9.5ns 4.75 1.5 ns wakeup from sleep mode (note 4) 0.18 wake-up time t wake wakeup from shutdown (note 4) 1.5 s channel-to-channel matching crosstalk f ina or b = 20mhz at -0.5db fs -70 db gain matching f ina or b = 20mhz at -0.5db fs 0.02 0.2 db phase matching f ina or b = 20mhz at -0.5db fs 0.25 degrees electrical characteristics (continued) (v dd = +3.3v, ov dd = +2.5v; 0.1f and 1.0f capacitors from refp, refn, and com to gnd; refout connected to refin through a 10k ? resistor, v in = 2v p-p (differential w.r.t. com), c l = 10pf at digital outputs (note 5), f clk = 105.263mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) note 1: snr, sinad, thd, sfdr, and hd3 are based on an analog input voltage of -0.5db fs, referenced to a +1.024v full-scale input voltage range. note 2: intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. this number i s 6db or better, if referenced to the two-tone envelope. note 3: digital outputs settle to v ih , v il . parameter guaranteed by design. note 4: with refin driven externally, refp, com, and refn are left floating while powered down. note 5: equivalent dynamic performance is obtainable over full ov dd range with reduced c l .
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 6 _______________________________________________________________________________________ typical operating characteristics (v dd = +3.3v, ov dd = +2.5v, internal reference, differential input at -0.5db fs, f clk = 105.0005678mhz, c l 10pf. t a = +25 c, unless otherwise noted.) -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 fft plot cha (8192-point record, differential input) max1180 toc01 analog input frequency (mhz) amplitude (db) cha f ina = 6.242099mhz f inb = 7.523844mhz f clk = 105.00057mhz aina = -0.52db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 fft plot chb (8192-point record, differential input) max1180 toc02 analog input frequency (mhz) amplitude (db) chb f ina = 6.242099mhz f inb = 7.523844mhz f clk = 105.00057mhz ainb = -0.48db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 fft plot cha (8192-point record, differential input) max1180 toc03 analog input frequency (mhz) amplitude (db) cha f ina = 20.084947mhz f inb = 25.006849mhz f clk = 105.00057mhz aina = -0.54db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 fft plot chb (8192-point record, differential input) max1180 toc04 analog input frequency (mhz) amplitude (db) chb f ina = 20.084947mhz f inb = 25.006849mhz f clk = 105.00057mhz aina = -0.54db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 fft plot cha (8192-point record, differential input) max1180 toc05 analog input frequency (mhz) amplitude (db) cha f ina = 52.23259mhz f inb = 57.050479mhz f clk = 105.00057mhz aina = -0.47db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 fft plot chb (8192-point record, differential input) max1180 toc06 analog input frequency (mhz) amplitude (db) chb f ina = 52.23259mhz f inb = 57.050479mhz f clk = 105.00057mhz ainb = -0.47db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 020 10 30 40 50 60 two-tone imd plot (8192-point record, differential input) max1180 toc07 analog input frequency (mhz) amplitude (db) f in1 f ina = 38.055015mhz f inb = 41.925886mhz f clk = 105.00057mhz ain = -6.5db fs two-tone envelope = -0.51db fs f in2 2nd order imd 3rd order imd 3rd order imd 60 54 110100 signal-to-noise ratio vs. analog input frequency 55 max1180 toc08 analog input frequency (mhz) snr (db) 56 57 58 59 chb cha differential input configuration 61 53 1 10 100 signal-to-noise + distortion vs. analog input frequency 55 max1180 toc09 analog input frequency (mhz) sinad (db) 57 59 differential input configuration chb cha
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = +3.3v, ov dd = +2.5v, internal reference, differential input at -0.5db fs, f clk = 105.0005678mhz, c l 10pf. t a = +25 c, unless otherwise noted.) -64 -74 110100 total harmonic distortion vs. analog input frequency -72 max1180 toc10 analog input frequency (mhz) thd (db) -70 -68 -66 cha chb differential input configuration 76 64 110100 spurious-free dynamic range vs. analog input frequency 66 max1180 toc11 analog input frequency (mhz) sfdr (db) 68 70 72 74 chb cha differential input configuration 6 -8 1 100 1000 full-power input bandwidth vs. analog input frequency, single-ended -4 -6 -2 0 2 4 max1180 toc12 analog input frequency (mhz) gain (db) 10 6 -8 1 100 1000 small-signal input bandwidth vs. analog input frequency, single-ended -4 -6 -2 0 2 4 max1180 toc13 analog input frequency (mhz) gain (db) 10 v in = 100mvp-p -12 -16 -20 -4 -8 0 signal-to-noise ratio vs. input power (f in = 20.084947mhz) max1180 toc14 input power (db fs) snr (db) 40 45 50 35 60 65 55 -12 -16 -20 -4 -8 0 signal-to-noise + distortion vs. input power (f in = 20.084947mhz) max1180 toc15 input power (db fs) sinad (db) 40 45 50 35 60 65 55 -16 -20 -4 -8 -12 0 total harmonic distortion vs. input power (f in = 20.084947mhz) max1180 toc16 input power (db fs) thd (db) -75 -70 -80 -60 -55 -65 -16 -20 -4 -8 -12 0 spurious-free dynamic range vs. input power (f in = 20.084947mhz) max1180 toc17 input power (db fs) sfdr (db) 64 68 60 76 80 72 -1.0 -0.5 0 0.5 1.0 0 256 512 768 128 384 640 896 1024 integral nonlinearity (best endpoint fit) max1180 toc18 digital output code inl (lsb)
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +3.3v, ov dd = +2.5v, internal reference, differential input at -0.5db fs, f clk = 105.0005678mhz, c l 10pf. t a = +25 c, unless otherwise noted.) -0.50 -0.25 0 0.25 0.50 0 256 512 768 128 384 640 896 1024 differential nonlinearity max1180 toc19 digital output code dnl (lsb) 1.0 0.5 0 -0.5 -1.0 -40 10 -15 35 60 85 offset error vs. temperature, external reference (v refin = +2.048v) max1180 toc20 temperature ( c) offset error (%fs) chb cha -1.5 -1.0 0 -0.5 0.5 1.0 -40 10 -15 35 60 85 gain error vs. temperature, external reference (v refin = +2.048v) max1180 toc21 temperature ( c) gain error (%fs) chb cha 44 40 56 52 48 60 sfdr, snr, thd, sinad vs. clock duty cycle max1180 toc25 clock duty cycle (%) sfdr, snr, thd, sinad (db) 50 60 40 80 90 70 sfdr thd snr sinad f in = 20.08495mhz 2.85 2.70 3.45 3.30 3.15 3.00 3.60 internal reference voltage vs. analog supply voltage max1180 toc26 v dd (v) v refout (v) 2.034 2.038 2.030 2.046 2.050 2.042 2.85 2.70 3.45 3.30 3.15 3.00 3.60 analog supply current vs. analog supply voltage max1180 toc22 v dd (v) i vdd (ma) 110 120 100 140 150 130 -15 -40 60 35 10 85 analog supply current vs. temperature max1180 toc23 temperature ( c) i vdd (ma) 110 120 100 140 150 130 2.85 2.70 3.45 3.30 3.15 3.00 3.60 analog power-down current vs. analog power supply max1180 toc24 v dd (v) i vdd ( a) 0.2 0.4 0 0.8 1.0 0.6 oe = pd = ov dd
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dd = +3.3v, ov dd = +2.5v, internal reference, differential input at -0.5db fs, f clk = 105.0005678mhz, c l 10pf. t a = +25 c, unless otherwise noted.) -15 -40 60 35 10 85 internal reference voltage vs. temperature max1180 toc27 temperature ( c) v refout (v) 2.025 2.035 2.015 2.055 2.065 2.045 n n-1 n-2 n+2 n+1 output noise histogram (dc input) max1180 toc28 digital output noise counts 1000 2000 3000 4000 0 6000 7000 5000 64676 607 00 252 pin description pin name function 1 com common-mode voltage input/output. bypass to gnd with a 0.1f capacitor. 2, 6, 11, 14, 15 v dd analog supply voltage. bypass to gnd with a capacitor combination of 2.2f in parallel with 0.1f. 3, 7, 10, 13, 16 gnd analog ground 4 ina+ channel a positive analog input. for single-ended operation, connect signal source to ina+. 5 ina- channel a negative analog input. for single-ended operation, connect ina- to com. 8 inb- channel b negative analog input. for single-ended operation, connect inb- to com. 9 inb+ channel b positive analog input. for single-ended operation, connect signal source to inb+. 12 clk converter clock input 17 t/b t/b selects the adc digital output format. high: two s complement. low: straight offset binary. 18 sleep sleep mode input. high: deactivates the two adcs, but leaves the reference bias circuit active. low: normal operation. 19 pd power-down input. high: power-down mode low: normal operation 20 oe output enable input. high: digital outputs disabled low: digital outputs enabled
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 10 ______________________________________________________________________________________ pin description (continued) pin name function 21 d9b three-state digital output, bit 9 (msb), channel b 22 d8b three-state digital output, bit 8, channel b 23 d7b three-state digital output, bit 7, channel b 24 d6b three-state digital output, bit 6, channel b 25 d5b three-state digital output, bit 5, channel b 26 d4b three-state digital output, bit 4, channel b 27 d3b three-state digital output, bit 3, channel b 28 d2b three-state digital output, bit 2, channel b 29 d1b three-state digital output, bit 1, channel b 30 d0b three-state digital output, bit 0 (lsb), channel b 31, 34 ognd output driver ground 32, 33 ov dd output driver supply voltage. bypass to ognd with a capacitor combination of 2.2f in parallel with 0.1f. 35 d0a three-state digital output, bit 0 (lsb), channel a 36 d1a three-state digital output, bit 1, channel a 37 d2a three-state digital output, bit 2, channel a 38 d3a three-state digital output, bit 3, channel a 39 d4a three-state digital output, bit 4, channel a 40 d5a three-state digital output, bit 5, channel a 41 d6a three-state digital output, bit 6, channel a 42 d7a three-state digital output, bit 7, channel a 43 d8a three-state digital output, bit 8, channel a 44 d9a three-state digital output, bit 9 (msb), channel a 45 refout internal reference voltage output. may be connected to refin through a resistor or a resistor divider. 46 refin reference input. v refin = 2 ? (v refp - v refn ). bypass to gnd with a >1nf capacitor. 47 refp positive reference input/output. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1f capacitor. 48 refn negative reference input/output. conversion range is (v refp - v refn ). bypass to gnd with a > 0.1f capacitor.
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 11 detailed description the max1180 uses a nine-stage, fully-differential pipelined architecture (figure 1), that allows for high- speed conversion while minimizing power consump- tion. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. counting the delay through the output latch, the clock- cycle latency is five clock cycles. 1.5-bit (two-comparator) flash adcs convert the held- input voltages into a digital code. the digital-to-analog converters (dacs) convert the digitized results back into analog voltages, which are then subtracted from the original held-input signals. the resulting error sig- nals are then multiplied by two and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all nine stages. digital error correction compensates for adc comparator offsets in each of these pipeline stages and ensures no missing codes. input track-and-hold (t/h) circuits figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuits in both track-and- hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a and s5b are closed. the fully-differential cir- cuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the amplifier input, and open simultaneously with s1, sampling the input wave- form. switches s4a and s4b are then opened before switches s3a and s3b, connect capacitors c1a and c1b to the output of the amplifier, and switch s4c is closed. the resulting differential voltages are held on capacitors c2a and c2b. the amplifiers are used to charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. the wide input bandwidth t/h amplifiers allow the max1180 to track- and-sample/hold analog inputs of high frequencies (> nyquist). both adc inputs (ina+, inb+, ina-, and inb-) can be driven either differentially or single-ended. match the impedance of ina+ and ina-, as well as inb+ and inb-, and set the common-mode voltage to midsupply (v dd /2) for optimum performance. analog inputs and reference configurations the full-scale range of the max1180 is determined by the internally generated voltage difference between refp (v dd /2 + v refin /4) and refn (v dd /2 - v refin /4). the full-scale range for both on-chip t/h v out x2 flash adc dac 1.5 bits 10 v ina v in stage 1 stage 2 d9a?0a v ina = input voltage between ina+ and ina- (differential or single-ended) v inb = input voltage between inb+ and inb- (differential or single-ended) digital correction logic stage 8 stage 9 2-bit flash adc t/h t/h v out x2 flash adc dac 1.5 bits 10 v inb v in stage 1 stage 2 d9b?0b digital correction logic stage 8 stage 9 2-bit flash adc t/h figure 1. pipelined architecture?tage blocks
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 12 ______________________________________________________________________________________ adcs is adjustable through the refin pin, which is provided for this purpose. refout, refp, com (v dd /2), and refn are internally buffered low-impedance outputs. the max1180 provides three modes of reference oper- ation: internal reference mode buffered external reference mode unbuffered external reference mode in the internal reference mode, connect the internal ref- erence output refout to refin through a resistor (e.g., 10k ? ) or resistor divider, if an application s3b s3a com s5b s5a inb+ inb- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a ina+ ina- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b max1180 figure 2. max1180 t/h amplifiers
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 13 requires a reduced full-scale range. for stability and noise filtering purposes, bypass refin with a >10nf capacitor to gnd. in internal reference mode, refout, com, refp, and refn become low-impedance out- puts. in the buffered external reference mode, adjust the ref- erence voltage levels externally by applying a stable and accurate voltage at refin. in this mode, com, refp, and refn become outputs. refout may be left open or connected to refin through a >10k ? resistor. in the unbuffered external reference mode, connect refin to gnd. this deactivates the on-chip reference buffers for refp, com, and refn. with their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources. clock input (clk) the max1180 s clk input accepts cmos-compatible clock signals. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). in particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. any significant aperture jitter would limit the snr perfor- mance of the on-chip adcs as follows: differential input voltage* differential input straight offset binary t/b = 0 two s complement t/b = 1 v ref ? 511/512 +full scale - 1lsb 11 1111 1111 01 1111 1111 v ref ? 1/512 + 1 lsb 10 0000 0001 00 0000 0001 0 bipolar zero 10 0000 0000 00 0000 0000 -v ref ? 1/512 - 1 lsb 01 1111 1111 11 1111 1111 -v ref ? 511/512 -full scale + 1 lsb 00 0000 0001 10 0000 0001 -v ref ? 512/512 -full scale 00 0000 0000 10 0000 0000 table 1. max1180 output codes for differential inputs n - 6 n n - 5 n + 1 n - 4 n + 2 n - 3 n + 3 n - 2 n + 4 n - 1 n + 5 n n + 6 n + 1 5 clock-cycle latency analog input clock input data output d9a d0a t d0 t ch t cl n - 6 n - 5 n - 4 n - 3 n - 2 n - 1 n n + 1 data output d9b d0b figure 3. system timing diagram *v ref = v refp ?v refn
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 14 ______________________________________________________________________________________ snr db = 20 ? log 10 (1 / [2 x f in ? t aj ]), where f in represents the analog input frequency and t aj is the time of the aperture jitter. clock jitter is especially critical for undersampling applications. the clock input should always be consid- ered as an analog input and routed away from any ana- log input or other digital signal lines. the max1180 clock input operates with a voltage thresh- old set to v dd /2. clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the electrical characteristics. system timing requirements figure 3 depicts the relationship between the clock input, analog input, and data output. the max1180 samples at the rising edge of the input clock. output data for channels a and b is valid on the next rising edge of the input clock. the output data has an internal latency of five clock cycles. figure 4 also determines the relationship between the input clock parameters and the valid output data on channels a and b. digital output data, output data format selection (t/b), output enable ( oe ) all digital outputs, d0a d9a (channel a) and d0b d9b (channel b), are ttl/cmos logic-compatible. there is a five clock cycle latency between any particular sam- ple and its corresponding output data. the output cod- ing can be chosen to be either straight offset binary or two s complement (table 1) controlled by a single pin (t/b). pull t/b low to select offset binary and high to activate two s complement output coding. the capaci- tive load on the digital outputs d0a d9a and d0b d9b should be kept as low as possible (<15pf), to avoid large digital currents that could feed back into the ana- log portion of the max1180, thereby degrading its dynamic performance. using buffers on the digital out- puts of the adcs can further isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the max1180 small-series resistors (e.g., 100 ? ), add to the digital output paths, close to the max1180. figure 4 displays the timing relationship between out- put enable and data output valid, as well as power- down/wake-up and data output valid. power-down (pd) and sleep (sleep) modes the max1180 offers two power-save modes, sleep and full power-down mode. in sleep mode (sleep = 1), only the reference bias circuit is active (both adcs are disabled) and current consumption is reduced to 2.8ma. to enter full power-down mode, pull pd high. with oe simultaneously low, all outputs are latched at the last value prior to the power-down. pulling oe high, forces the digital outputs into a high-impedance state. applications information figure 5 depicts a typical application circuit containing two single-ended to differential converters. the internal reference provides a v dd /2 output voltage for level- shifting purposes. the input is buffered and then split to a voltage follower and inverter. one lowpass filter per adc suppresses some of the wideband noise associat- ed with high-speed operational amplifiers. the user may select the r iso and c in values to optimize the filter performance to suit a particular application. for the application in figure 5, a r iso of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor. using transformer coupling an rf transformer (figure 6) provides an excellent solution to convert a single-ended source signal to a fully-differential signal, required by the max1180 for optimum performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. although a 1:1 transformer is shown, a step- up transformer may be selected to reduce the drive requirements. a reduced signal swing from the input driver, such as an op amp, may also improve the over- all distortion. in general, the max1180 provides better sfdr and thd with fully-differential input signals, than a single- ended drive, especially for high input frequencies. in differential input mode, even-order harmonics are lower as both inputs (ina+, ina- and/or inb+, inb-) are bal- output d9a d0a oe t disable t enable high-z high-z valid data output d9b d0b high-z high-z valid data figure 4. output timing diagram
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 15 input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f -5v 600 ? 300 ? 300 ? ina+ ina- lowpass filter com 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 max1180 inb+ inb- max4108 max4108 lowpass filter input 300 ? -5v +5v 0.1 f 0.1 f 0.1 f c in 22pf -5v 600 ? 300 ? 300 ? lowpass filter 600 ? +5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f +5v 0.1 f 300 ? max4108 max4108 max4108 lowpass filter r iso 50 ? c in 22pf r iso 50 ? c in 22pf r iso 50 ? c in 22pf r iso 50 ? figure 5. typical application for single-ended to differential conversion
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 16 ______________________________________________________________________________________ anced, and each of the adc inputs only require half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 7 shows an ac-coupled, single-ended applica- tion. amplifiers, like the max4108, provide high-speed, high bandwidth, low-noise, and low distortion to main- tain the integrity of the input signal. typical qam demodulation application the most frequently used modulation technique for dig- ital communications application is the quadrature amplitude modulation (qam). qams are typically found in spread-spectrum based systems. a qam signal rep- resents a carrier frequency modulated in both ampli- tude and phase. at the transmitter, modulating the baseband signal with quadrature outputs, a local oscil- lator followed by subsequent up-conversion can gener- ate the qam signal. the result is an in-phase (i) and a quadrature (q) carrier component, where the q compo- nent is 90 degrees phase-shifted with respect to the in- phase component. at the receiver, the qam signal is divided down into its i and q components, essentially representing the modulation process reversed. figure 8 displays the demodulation process performed in the analog domain, using the dual-matched, +3v, 10-bit adcs, max1180 and the max2451 quadrature demod- ulators, to recover and digitize the i and q baseband signals. before being digitized by the max1180, the mixed-down signal components may be filtered by matched analog filters, such as nyquist or pulse- shaping filters which remove any unwanted images from the mixing process, enhances the overall signal- to-noise (snr) performance, and minimizes intersym- bol interference. grounding, bypassing, and board layout the max1180 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side as the adc, using surface-mount devices for minimum inductance. bypass v dd , refp, refn, and com with two parallel 0.1f ceramic capacitors and a 2.2f bipolar capacitor to gnd. follow the same rules to bypass the digital supply (ov dd ) to ognd. multilayer boards with separate ground and power planes, pro- duce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of the analog ground (gnd) and the digital output driver ground (ognd) on the adcs pack- age. the two ground planes should be joined at a sin- gle point, such that the noisy digital ground currents do not interfere with the analog ground plane. the ideal location of this connection can be determined experi- mentally at a point along the gap between the two ground planes, which produces optimum results. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from the sensitive analog traces of either channel. make sure to isolate the analog input lines to each respective converter to max1180 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1 6 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 0.1 f 0.1 f 2.2 f 25 ? 25 ? minicircuits tt1 6 ina- ina+ inb- inb+ com figure 6. transformer-coupled input drive
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 17 max1180 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf inb+ inb- com ina+ ina- 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in max4108 figure 7. using an op amp for single-ended, ac-coupled input drive 0 90 8 downconverter max2451 ina+ max1180 ina- inb+ inb- dsp post processing figure 8. typical qam application, using the max1180
minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 degree turns. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the max1180 are measured using the best straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step-width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. dynamic parameter definitions aperture jitter figure 9 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 9). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n-bits): snr db[max] = 6.02 db ? n + 1.76 db in reality, there are other noise sources besides quanti- zation noise; thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc s error consists of quantization noise only. enob is computed from: total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? 20 10 2222 1 2345 log enob sinad db db db = ? 176 602 . . max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs 18 ______________________________________________________________________________________ hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 9. t/h aperture timing
intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale and their envelope is at -0.5db full scale. chip information transistor count: 10,811 process: cmos max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs ______________________________________________________________________________________ 19 gnd reference output drivers control t/h t/h pipeline adc dec output drivers refout refn com refp refin ina+ ina- clk inb+ inb- v dd dec pipeline adc ognd ov dd d9a d0a oe d9b d0b 10 10 10 10 t/b pd sleep max1180 functional diagram
max1180 dual 10-bit, 105msps, +3.3v, low-power adc with internal reference and parallel outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information 48l,tqfp.eps

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